1. Technical Field
The present invention relates to a semiconductor component.
2. Description of Related Art
Reducing the area-specific on resistance Ron·A is of great importance in the further development of a large number of semiconductor components, particular consideration being given in this case to, in particular, the field of power semiconductor components and the so-called DMOS power transistors in this field. In this case one of the essential objectives besides lowering the area-specific on resistance Ron·A is simultaneously forming a good breakdown or avalanche strength of the semiconductor component respectively fabricated.
Although there are indeed measures that promise much, e.g. the so-called field plate concept, for providing corresponding architectures which can realize these component properties, these known concepts by themselves are not sufficiently, particularly in the edge region of a chip or of a cell array on a chip, in order to enable the required properties described above to be realized in a simple manner in the case of a power semiconductor component.
Therefore, the invention is based on the object of specifying a semiconductor component in which, even in the edge region of a chip or cell array, it is possible to achieve particularly favorable properties with regard to the on resistivity and the breakdown strength or avalanche strength without a high outlay.